EDN

VLSI confab melds explorations of semi process, design issues

MANHASSET, N.Y. — The interdependence between process and design is in full evidence at this year's VLSI Symposia, being held June 17-20 in Honolulu, Hawaii. The Symposium on VLSI Technology straddles ...
IPWatchdog

Vidal to Review Institution of Cases Against VLSI Under Interim Director Review Process

“The cases ‘[raise] novel issues of law and policy, as well as issues of particular importance to the Office and the patent community.’” – Vidal Orders Granting Director Review Vidal explained in ...
Nature

Hotspot Detection and Machine Learning in VLSI Design

Advances in very-large-scale integration (VLSI) design have increasingly relied on machine learning (ML) techniques to optimise performance, reduce manufacturing turnaround times and ensure high ...
The Verge

Intel’s backside power delivery process could make CPUs a whole lot more efficient

The company beat its competitors to this style of manufacturing. The company beat its competitors to this style of manufacturing. is a former weekend editor who covered tech and entertainment. He has ...
EDN

VLSI: Intel’s 32-nm process ready for RF

SAN JOSE, Calif. — At this week's 2010 Symposium on VLSI Circuits in Hawaii, Intel Corp. has put a new twist on its previously-announced 32-nm process: It claims the technology is suitable for ...